Node loop core for implementing transmission protocol in fibre channel

ABSTRACT

Disclosed is a node loop port core for use in a Fibre Channel high speed data system for implementing transmission protocol and loop arbitration. The node loop core converts incoming data from 10 bit format to 8 bit format, checks frame CRC, parses frames, and steers the results to any one of a number of buffers. The buffers function as loading areas for incoming frames and are not part of NL core. In transmit operation, the node loop core chooses a loaded buffer to service, assembles frames, generates and adds CRC to frames, encodes the result from 8 bit to 10 bit format and then transfers the results. All control functions associated with primitive signals and sequences are handled by the node loop core. The core follows established Fibre Channel arbitration rules and recognizes all necessary primitive signals and primitive sequences for proper operation of the arbitrated loop.

CROSS-REFERENCE TO RELATED APPLICATION

This patent application is related to application Ser. No. 08/329,032,filed Oct. 24, 1994, now U.s. Pat. No. 5,598,541, filed concurrentlyherewith for NODE LOOP PORT SUPER CORE FOR USE IN FIBRE CHANNEL.

BACKGROUND OF THE INVENTION

This invention relates generally to data communication and processing,and more particularly the invention relates to a Node Loop Core forimplementing the transmission protocol in a Fibre Channel Node Port andwhich is flexible in structure and in operation with a Node Loop PortSuper Core for implementing the Fibre Channel Standard as adopted byANSI.

The Fibre Channel Standard (FCS) as adopted by ANSI provides a low cost,high speed interconnect standard for workstations, mass storage devices,printers, and displays. The Fibre Channel (FC) is ideal for distributedsystem architectures and image intensive LANs and clusters. FC is mediaindependent and provides multi-vendor interoperability.

Current FC transfer rates exceed 100 Mbytes per second in eachdirection. FC data transfer rates can also be scaled to 50, 25, and 12.5Mbytes per second. The aggregate bandwidth is unlimited.

Fibre Channel technology provides a single interface that supports bothchannel and network connections for both switched and shared mediums. FCsimplifies device interconnections and software, and reduces hardwarecosts since each device needs only a single FC port for both channel andnetwork interfaces. Network, point to point, and peripheral interfacescan be accessed through the same hardware connection with the transferof data of any format for the sending device buffer to the receivingdevice buffer.

FCS can also be implemented using a low-cost Arbitrated Loopconfiguration. The aggregate bandwidth is limited by the FC maximumbandwidth, but this is the best configuration for controlling diskarrays. The Node Loop Port (NL₋₋ Port) provides the necessary functionsfor Arbitrated Loop.

FIGS. 1A-1D illustrate several topologies for implementing the FibreChannel.

FIG. 1A illustrates a Point-to-Point topology. FIG. 1B shows a simplefabric topology. FIG. 1C shows a Closed Arbitrated Loop, and FIG. 1Dillustrates an Open Arbitrated Loop. The fabric link in FIG. 1D usescircuit switching much like a telephone network. The FC createsmultiple, temporary, direct connections that each provide fullbandwidth. Further, the bandwidth can be expanded by adding more paths.

A Fibre Channel Fabric can be as simple as a single cable connecting twodevices or as complex as a large number of FC switches incorporatingboth circuit and packet switching that connect up to 16,000,000 devices.A device attached to an FC fabric can transmit data to any other deviceand receive data from any other device attached to the fabric.

An FC fabric uses circuit switching much like a telephone network. TheFC creates multiple, temporary, direct connections that each provide thefull bandwidth. Each connection can use the entire bandwidth so it doesnot become congested by adding more workstations and peripherals. Thebandwidth can be expanded by adding more paths.

The FC hardware routes the transmissions. A device connected to thefabric that wants to transmit requests connection to the receivingdevice. The FC attempts to route the call by querying the availabilityof the receiving device. If the device responds that it is available,the FC confirms the route back to the sending device. If the connectionfails, the FC re-routes the transmission.

Setting up frequent connections is not time intensive (less than 10 μsper connection).

Every Node Port logs in with the port to which it is attached, either anF₋₋ Port or an N₋₋ Port.

The Fibre Channel Standard includes bridges and routers that cansimultaneously transport other data communications protocols, so alreadyexisting devices need only be enhanced by attaching adapters rather thanbeing replaced. The FCS provides for new media technologies to be easilyadded. Currently the FCS provides interconnection to the followinghigher-level protocols:

FDDI (Fibre Distributed Data Interface)

HIPPI (High Performance Parallel Interface)

SCSI (Small Computer Systems Interface)

IPI (Intelligent Peripheral Interface)

IBM's Block Multiplexer Channel

ATM (In process)

FC is a solution to the following applications that require large volumeinformation storage and transfers:

Medical Imaging

Engineering CAD

Scientific Visualization

Computer Generated 3D Animation and Full-motion Video

Simulation

Multimedia

Video Conferencing

Image-based Document Storage and retrieval

Large Transaction Databases

Off-site Large Volume Backups--decouples mass storage from CPU--simple,quick, offsite backup

Communications Channels for Supercomputer Emulation (workstationclustering)

These applications require data transfers up to Mbits per second (3032-bit color 1024×768 pixel images per second) uncompressed. Most of thecurrent connection technologies are unable to transfer data fast enoughto meet these needs. Fibre Channel can transfer uncompressed video dataat rates that can generate full-screen real-time color displays.

The following tables define the Fibre Channel Standard (FCS levels(layers).

    ______________________________________                                        FC                                                                            Level Description                                                                              Defines:                                                     ______________________________________                                        FC-0  Physical   Optical and electrical parameters                                  Interface  for interfacing to a variety of                                               physical media that operate over a                                            wide range of data rates                                     FC-1  Transmission                                                                             Serial encoding, decoding, and                                     Protocol   error control (8-bit/10-bit code)                            FC-2  Signaling  Frame structures and byte sequences                                (Framing)  used by FC-4 to transfer data                                      Protocol   (transport mechanism)                                        FC-3  Common     a set of services that are common                                  Services   across multiple N.sub.-- Ports of an FC node                 FC-4  Mapping to Software mapping between the FC                                    Upper-Level                                                                              lower levels (FC-0,1,2,3) and the                                  Protocols  upper-level protocols (IP13, SCSI,                                            IP etc.)                                                     ______________________________________                                    

Following are brief definitions of some of the FCS Framing Protocol(FC-2) terminology.

Two possible FC frame formats with FC frames being separated from eachother by at least six four-byte IDLEs.

Following are illustrations of two Fibre Channel frames with a tabledefining the frame fields:

    ______________________________________                                        SOF   FHDR      Payload         CRC   EOF                                               or                                                                  SOF   FHDR      OHDR     Payload  CRC   EOF                                   ______________________________________                                        Mnemonic    Definition      Size (Bytes                                       ______________________________________                                        SOF         Start of Frame  4                                                 FHDR        Frame Header    24                                                OHDR        Optional Headers                                                                              64 or 0                                           Payload     Data            2112 or 2048                                      CRC         Frame Error Check                                                                             4                                                 EOF         End of Frame    4                                                 ______________________________________                                    

Each frame is an indivisible unit of information used by the signalingprotocol (FC-2) and there are four major FC-2 frame types:

Device₋₋ Data frames carry data of the upper level protocol type.

Link₋₋ Data frames which carry a built-in protocol called Link Services.

Link₋₋ Control frames which implement flow control, error detection, anderror handling functions.

Video₋₋ Data frames which carry video data that is directed to a videobuffer.

The following table shows the FC-2 Frame Header (FHDR) structure:

    ______________________________________                                        Word    Byte 1    Byte 2      Byte 3 Byte 4                                   ______________________________________                                        1       R.sub.-- CTL                                                                            DESTINATION.sub.-- ID                                       2       Reserved  SOURCE.sub.-- ID                                            3       TYPE      F.sub.-- CTL                                                4       SEQ.sub.-- ID                                                                           DF.sub.-- CTL                                                                             SEQ.sub.-- CNT                                  5       OX.sub.-- ID      RX.sub.-- ID                                        6       PARAMETER                                                             ______________________________________                                    

The following table defines the FHDR R₋₋ CTL routing bits.

    ______________________________________                                        R.sub.-- CTL[7:4] Frame Definition                                            ______________________________________                                        0000              FC-4 Device.sub.-- Data                                     0010              Extended Link.sub.-- Data                                   0011              FC-4 Link.sub.-- Data                                       0100              Video.sub.-- Data                                           1000              Basic Link.sub.-- Data                                      1100              Link.sub.-- Control                                         All Others        Reserved                                                    ______________________________________                                    

FIG. 2 is a functional block diagram of the NL Core 10 and the SuperCore 12 which implement the FC-1 and FC-2 transmission and signallingprotocols of the Fibre Channel standard. Heretofore, these protocolshave been implemented with application specific integrated circuits(ASIC) with a host computer. This structure requires large and complexlogic and has proved to be limited in achieving the 80 Mbytes/secsustained throughput required.

The present invention provides a Node Loop Core for use in a modularsuper core structure with an imbedded processor which supports afull-featured Fibre Channel operation at 80 Mbytes/second sustainedthroughput. The structure can be designed in an application specificintegrated circuit with custom specific functions appended thereto.

SUMMARY OF THE INVENTION

The Node Loop Core in accordance with the invention includes a DecodeWord unit and an Encode₋₋ Word unit for interfacing with the FibreChannel Cable, an Arbitrated Loop, and Receive and Transmit Units forinterfacing with the Super Core for the transmission of data to and fromthe Fibre Channel Cable and attached apparatus.

The Decode Word unit functions to convert 10-bit data to 8-bit data witherror checking, recognize a comma character, and to construct parityprotected words from half-words or bytes.

The Encode₋₋ Word unit functions to convert 8-bit data to 10-bit encodeddata and generate the comma character for use with transmitted data. Theunit also checks parity error of input words and divides the words intohalf-words or bytes as programmed.

The Arbitrated Loop performs initialization protocol and arbitrationfunctions while recognizing all primitive signals and sequencespertinent to the loop.

The Receive Unit performs frame parsing and frame steering, errorchecking, primitive detection, and offset computation if offset is used.

The Transmit Unit provides frame construction from multiple sources, CRCgeneration, and primitive signal and sequence generation. The unit alsoimplements hardware managed sequences and provides the mechanism forsoftware managed single frame.

The Node Loop Port Core, in accordance with the invention, functionswith the Super Core in supporting an Arbitrated Loop topology inattaching multiple communicating ports in a loop without hubs andswitches and provides maximum possible data transfer bandwidth at thespeeds of 100, 50, 25, and 12.5 Mbits/second.

The invention and objects and features there of will be more readilyapparent from the following detailed description and appended claimswhen taken with the drawing.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1D are functional block diagrams illustrating topologies of theFibre Channel.

FIG. 2 is a functional block diagram of the NL Core and Super Core inimplementing the transmission and framing protocols of the Fibre ChannelStandard.

FIG. 3 is a functional block diagram of a Node Loop Core in accordancewith the invention.

FIG. 4 is a functional block diagram of the Decode₋₋ Word block of FIG.3.

FIG. 5 is a functional block diagram of the Encode₋₋ Word block of FIG.3.

FIG. 6 is a functional block diagram of the Arbitrated Loop block ofFIG. 3.

FIG. 7 is a functional block diagram of the Receive Block of FIG. 3.

FIG. 8 is a functional block diagram of the Transmit Block of FIG. 3.

FIG. 9 illustrates signals for bit level logic interface of the NodeLoop Core.

FIGS. 10A-10C are flow diagrams of a receive operation.

FIGS. 11A-11D are timing diagrams for reception of a class 1 frame,reception of class 2/3 receive frame, reception of a class 2/3 dataframe, and reception of a class 1 data frame, respectively.

FIG. 12 illustrates a receive word synchronization state machinediagram.

FIGS. 13A-13B are flow diagrams of a transmit operation.

FIGS. 14A-14D are timing diagrams for transmission of a single dataframe, transmission of a link frame, transmission of back-to-back framesfor a hardware managed sequence with optional headers present, and fortransmission of a frame in a hardware managed sequence when an optionalheader is not present, respectively.

FIG. 15 is a functional block diagram illustrating the flow controlmechanism.

FIG. 16 illustrates a transmit state diagram.

FIG. 17 illustrates a receive frame interface format (FIF).

FIG. 18 illustrates a transmit frame interface format.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENT

FIG. 3 is a functional block diagram of a Node Loop Core in accordancewith the invention. The basic functional blocks include a Decode₋₋ Wordunit 10 and an Encode₋₋ Word unit 12 which interface with the FibreChannel Cable through a serializer/deserializer unit (not shown). TheDecode₋₋ Word unit converts 10-bit to 8-bit data with error checking andperforms comma character recognition in incoming data stream. The unitalso constructs 32-bit parity protected words from half-words or bytesas programmed. Similarly, the Encode₋₋ Word unit converts 8-bit data to10-bit encoded data with comma character generation. The unit alsochecks parity error of input words and divides the words into half-wordsor bytes as programmed.

An Arbitrated Loop 14 interfaces with the Decode₋₋ Word unit 10 andEncode₋₋ Word unit 12 along with a Receive Unit 16 and a Transmit Unit18 and performs loop initialization protocol and loop arbitrationfunctions. The Arbitrated Loop recognizes all primitive signals andsequences pertinent to the loop and includes a Loop State Machine andLoop Buffer.

Receive Unit 16 functions in frame parsing, frame steering, CRC errorand logical error checking, primitive detection, and offset computationif offset is used.

The Transmit Block 18 performs frame construction from multiple sources,CRC generation, and primitive signal and sequence generation. The blockalso performs hardware managed sequences and software managed singleframe sequence. The block also provides data frame sequence transmissionand flow control.

FIG. 4 is a more detailed functional block diagram of the Decode₋₋ Wordblock of FIG. 3. The block includes a 20-bit input 40 which is thedirect 20-bit data path used when this mode is enabled. A 10-bit input42 is provided as the direct 10-bit data path when this mode is enabled.The input contains logic to convert the data path from 10 to 20 bits andto divide the incoming clock by 2. A decoder 44 contains two parallel10-bit to 8-bit decoders with full error checking. Detected errors areposted via the Decode₋₋ Word status interface. A parity generator 46operates and appends odd parity immediately after a decode, one paritybit per byte. This parity accompanies data throughout the NL Core.

A word assembler 48 assembles 32-bit parity protected data for theArbitrated Loop. The receive word control (r₋₋ word₋₋ cntl) 49 receivesstatus symbols and detects error signals and controls all operations inthe Decode₋₋ Word block.

FIG. 5 is a more detailed functional block diagram of the Encode₋₋ Wordblock 12 of FIG. 3. The block includes a 20-bit output 50 which providesthe direct 20-bit data path when this mode is enabled. A 10-bit output52 is a direct 10-bit data path when this mode is enabled. It containslogic to convert the data path from 10 to 20 bits and to divide theincoming clock by 2.

An Encoder 54 includes two parallel 8-bit to 10-bit encoders, and aparity checker 56 checks odd parity prior to encode and strips off theparity bit, one parity bit per byte.

Word Disassembler 58 disassembles 32-pit parity protected data into16-bit parity protected data for the parity checker and encoder logic.The transmit word controller (t₋₋ word₋₋ cntl) 59 receives statussignals and controls all the operations of the Encode₋₋ Word block. Thetransmit word clock (T₋₋ word₋₋ clk) is derived by this module using theT₋₋ clk input.

FIG. 6 illustrates the architecture of the Arbitrated Loop 14 of FIG. 3.A Loop State Machine 60 performs loop initialization protocol, looparbitration, and detects all ordered sets pertinent to the ArbitratedLoop. The Loop State Machine is used to acquire Arbitrated Loop physicaladdresses at Power On, and after loop initialization the NL₋₋ Port goesinto a monitoring state. When the loop is idle and the NL₋₋ Port wantsto communicate with another NL₋₋ Port, loop arbitration protocol isperformed by the Loop State Machine 60. When arbitration is won by anyloop port, all the intermediate loop ports act as repeaters oftransmission words. In this case, a loop buffer is used to provide theelasticity to re-time the data and send data to the transmitter. TheLoop State Machine also looks for the primitive sequence which indicatesthat the present Arbitrated Loop connection is over.

A Loop Buffer 62 is six words deep so that received words are re-timedand transmitted through the Encode₋₋ Word block and transmitter.

A MUX1 unit 64 is a 36-bit multiplexer and is controlled by the LoopState Machine. When the NL₋₋ Port is participating in the communicationwith another NL₋₋ Port, then the data is presented to downstream logicthrough the Receive Block. When the NL₋₋ Port is not participating inthe communication between any other two NL₋₋ Ports, the data ispresented to the Loop Buffer 62.

A MUX2 unit 66 is a 36-bit multiplexer and is controlled by the LoopState Machine. When the NL₋₋ Port is participating in the communicationwith another NL₋₋ Port, then the data is received from downstream logicthrough the Transmit Block. When the NL₋₋ Port is not participating inthe communication between any other NL₋₋ Ports, the data is receivedfrom Loop Buffer 62.

FIG. 7 illustrates the architecture of the Receive Block 16 of FIG. 3. ADetect Ordered Set 70 detects primitive signals, primitive sequences,and frame delimiters. A CRC Generate Check 71 (Cycle Redundancy Check)is a 32-bit parallel CRC check network. This block generates a CRC forincoming frames (data imbedded between Start Of Frame (SOF) and End OfFrame (EOF) and checks for correct CRC. Detected errors are posted viathe r₋₋ status interface.

Receive Pipe 72 provides decoded words for performing variouscomputations in the Receive Engine. The output word will be either thepipeline stages or from the Receive Control.

Steering Control 73 provides all logic signals, performs frame parsingand steering. In steering unmodified mode, all frames with nomodifications are presented to downstream logic so that custom steeringmechanisms may be implemented with the help of frame status symbols. Inthe steering header class scheme, the headers are steered into differentbuffers than the device data or video data payload. All headers aremodified for the convenience of the downstream logic using frameinterface formats. All basic link control frames are steered in entiretyto buffer to buffer flow control header buffers.

MUX 74 is a multiplier which provides data to the downstream logic. AllFrame Interface Format (FIF) header changes are provided to downstreamlogic through the multiplexer which is controlled by the Receive Control75.

The Frame Interface Formats unit 76 (FIF) converts frames from the FCSformat to FIF, if this option is programmed. The FIF modifies SOF word,EOF word, and inserts two new words before the EOF word. FIF modifiesthe SOF field by writing a SOF code in horizontal format to the headerHOF slot. At the completion of writing data to PL buffer, CRC is writtento the Header Buffer, then the base address if offset is used.

Frame control 77 provides all necessary frame parsing information todownstream logic, which can be used for the custom steeringimplementations.

The Base Address Register 78 provides the base address for vectoringdevice data or video data frames to RAM. This has to be programmed priorto reception of a first frame of a sequence. If offset is used, thestarting address for each new frame is computed and presented todownstream logic. The following table describes the function of the BaseAddress Register bits:

BAR Bits Description [31:0] Base byte address

This is used for Class 1 frame sequences. This can be used for Class 2sequences if sequence streaming is prohibited, and if the order ofdelivery is guaranteed. The FHDR sequence count is checked forvalidating all incoming Class 1 frames.

The Receive Control 75 provides all the required status signals to thedownstream logic and controls functional blocks in the receiveoperation.

FIG. 8 illustrates the architecture of the Transmit Block 18 of FIG. 3.The CRC Generate Unit 80 generates the CRC for every frame excluding SOFand EOF delimiters. CRC is transmitted through the output MUX justbefore EOF and is controlled by transmit control.

The Transmit Control Unit 81 controls all of the blocks in the transmitoperation. The major functions controlled by the Transmit Control are:

Single frames from the Frame Interface, through Payload FIFO.

A sequence of frames at the maximum FCS rate by utilizing the HMSmechanism. This is programmed using the register interface.

FCS Idles and Primitive Sequences

R₋₋ RDY₋₋ rcvd and Xmit₋₋ R₋₋ RDY for buffer-to-buffer flow control.

Frame delimiter generation, Frame Interface Formats option isprogrammed.

Offset generation for each data frame in the Hardware Managed Sequence(HMS), and transmitted as PARAMETER field in the frame headertransmission.

CRC generation and transmitting CRC just before EOF transmission.

BB Flow Control 82 contains mechanisms for hardware-managed R₋₋ RDY flowcontrol. A Credit Counter contains a four-bit count representing thenumber of outstanding BBFLO frames. The Credit Counter is comparedagainst a programmable Credit Limit that defines the number of BBFLObuffer in the remote link receiver. If the Credit Counter reaches theprogrammable limit, which means the remote link receiver has no openbuffer space, the NL₋₋ Core Transmit does not transmit any BBFLO framesuntil the remote link transmits a R₋₋ RDY signal. An R₋₋ RDY Counterkeeps an 8-bit count of outstanding R₋₋ RDYs to be transmitted. SignalIncrement₋₋ R₋₋ RDY is used for incrementing the counter. The NL₋₋ CoreTransmit sends all outstanding R₋₋ RDYs at the earliest possible moment.

The hardware sequencing parameters and registers 83 provides thenecessary parameters for hardware managed sequences. Frame header is of6 words, and the first frame header sent is stored in 6 word sizeregisters. A Hardware Managed Sequence Control register contains controlinformation for transmitting a hardware managed sequence. The followingtable describes bits of this register:

    ______________________________________                                        hms.sub.-- ctl Bits                                                                    Description                                                          ______________________________________                                        31       Relative Offset (RO) arithmetic                                               0 = Do not use Relative Offset                                                1 = Use of Relative Offset.sup.1                                     [30:29]  Sequence Count initialization                                                 00 = Set starting Frame Header SEQ.sub.-- CNT = 0                             01 = Set starting Frame Header SEQ.sub.-- CNT =                               last Frame Header                                                             SEQ.sub.-- CNT.sup.2                                                          10 = Set starting Frame Header SEQ.sub.-- CNT =                               first FHDR SEQ.sub.-- CNT                                                     11 = Not used                                                        [28:24]  Not used                                                             [23:0]   Frame Header F.sub.-- CTL [23:0] for first and last                           frame of sequence.sup.3                                              ______________________________________                                         .sup.1 When hms.sub.-- ctl31 = 1, relative offset is computed and placed      in the parameter field, through h.sub.-- wd5.sub.-- reg.                      .sup.2 Last FHDR SEQ.sub.-- CNT = value of the SEQ.sub.-- CNT of the last     frame of the last hardware managed sequence, plus 1.                          .sup.3 For the first frame of sequence, abort sequence policy has to be       transmitted. For all other frames, this field is not relevant. For the        last frame of a sequence, the content of the hms.sub.-- ctl[23.0] will be     used for F.sub.-- CTL. For all the intermediate frames, F.sub.-- CTL[23:0     is similar to that of the first frame. This information is extracted by       Transmit Control, and written in h.sub.-- wd2 reg.                       

The HMS control register provides the Sequence Count (plus one) of theprevious frame SEQ₋₋ CNT of a HMS. This value is necessary because theexact final Sequence Count cannot always be predicted ahead of time. TheRegister provides the starting Sequence Count for the next HMS if theSequence count of the next sequence is a continuation of the previoussequence.

Frame Data Mux 84 multiplexes the data the and the headers of a frame.The output of this multiplexer is fed to the CRC Generate. In thesteering₋₋ unmodified case, the header and payload come from the payloadbuffer. In steering₋₋ header₋₋ class case, the header comes form theHeader MUX and the data from the Payload. This multiplexer is controlledby Transmit Control.

Header Mux 85 multiplexes the frame header from different sourcesdepending on the class of service. If the hardware managed sequence isselected for a single sequence of any class, the header is selected formthe Hardware Sequencing Parameters and the Registers blocks. Otherwise,the header is read from the hc1 port for class 1 frames and hc23 portfor class 2/3. The multiplexer is controlled by Transmit Control 89.

The Output Mux 86 is the final multiplexer of the transmission words,before the words are presented to the Encode block through themultiplexer in the Arbitrated Loop. The multiplexer has three datapaths; one path provides header and data, one provides SOF and EOF, andthe third provides CRC to be transmitted just before EOF. The secondpath, which provides SOF and EOF delimiters, also provides primitivesequence and signal transmission.

PSSD Generation Block 87 performs Primitive Signal, Sequence, andDelimiter generation. Whenever primitive signal or primitive sequence orSOF/EOF delimiter is to be transmitted, the Xmit₋₋ k28.5 signal isasserted.

Steering Control 88 provides various control signals required to controlconstruction of frames from multiple sources depending on user selectedsteering mechanisms.

FIG. 9 illustrates the signal which comprise the bit level (logical)interface of the Fibre Channel NL₋₋ Port Core. The following is adescription of the signals:

    __________________________________________________________________________    Decode Word Signals                                                                      The Decode Word Module Interface receives all incoming signals                from the Fiber Optic Module (FOM).                                            This includes recovered receive data, data width control, and                 status from both the transmit and receive FOMs.                               FDB.sub.-- IN[19:0]                                                                        FOM Data In                     Input                                         These signals contain two 10-bit FCS characters                               from the FOM.                                                                 See subsection entitled "Decode.sub.-- word                                   Interface Formats" on                                                         page 4-24 for the pin format.                                    BYTE.sub.-- SYNC                                                                           FOM Byte Sync                   Input                                         Asserting this signal indicates that there is a                               Special Character                                                             (the first character of all ordered sets) or a                                comma to be read on                                                           FDB.sub.-- IN[19:0]. The FOM should assert this                               signal HIGH every                                                             time it detects a comma character.                               LASER.sub.-- STATUS                                                                        FOM Transmitter Laser Fault     Input                                         Asserting this signal HIGH indicates that the FOM                             transmitter is                                                                detecting no laser output. The Receive passes                                 this signal along                                                             as the STATUS.sub.-- REG10 output.                               LINK.sub.-- STATUS                                                                         FOM Receiver Loss of Light (Open                                                                              Input)                                        Asserting this signal HIGH indicates that the FOM                             receiver is                                                                   detecting no signal. This signal is an input into                             the Receive State                                                             Machine. The Receive passes this signal along as                              the                                                                           STATUS.sub.-- REG9 output.                                       UL.sub.-- SELECT                                                                           10 bit upper/lower select       input                                         When using 10bit FOMs, this input selects whether                             the 10bit                                                                     FOM input to the Receive is received in the upper                             10bits or the                                                                 lower 10bits of the 20bit FDB.sub.-- IN[19:0]                                 interface.                                                       10.sub.-- 20.sub.-- SELECT                                                                 10bit/20bit select              input                                         Asserting this signal HIGH configures the Receive                             to accept                                                                     10bit FOM inputs. Deasserting this signal LOW                                 configures the                                                                Receive to accept 20bit FOM inputs.                   Encode Word Signals                                                                      The Encode Word Module Interface provides all outgoing data                   and control signals to the FOM. This includes                                 the parallel transmission data and control for both the                       transmit and receive FOMs.                                                    LINK.sub.-- CONTROL                                                                        Enable FOM Laser                Output                                        The Encode assserts this signal HIGH to turn on                               the FOM transmit                                                              laser.                                                           LOCK.sub.-- REF                                                                            Enable FOM Lock to Reference    Output                                        The Encode asserts this signal HIGH to force the                              receive Phase                                                                 Lock Loop (PLL) to lock to the reference                                      oscillator.                                                      LOOP.sub.-- ENABLE                                                                         FOM Loop-Back Enable            Output                                        The Encode asserts this signal HIGH to route FOM                              output to                                                                     FOM input.                                                       ENCODE.sub.-- TYPE                                                                         FOM Type Select                 Input                                         Asserting this signal HIGH configures the Encode                              to send 10-bit                                                                FOM outputs. Deasserting this signal LOW                                      configures the                                                                Encode to send 20-bit FOM outputs.                               LOOP.sub.-- CTL                                                                            FOM Loop-Back control           Input                                         Asserting this signal HIGH enables Encode to                                  generate                                                                      LOOP.sub.-- ENABLE signal. This a active in both                              10 bit and 20 bit                                                             mode.                                                            LOCK.sub.-- REF.sub.-- CTL                                                                 FOM Lock to Reference Control   Input                                         Asserting this signal HIGH enable Encode to drive                             LOCK.sub.-- REF                                                               output pin in either 10bit or 20bit mode.                        LASER.sub.-- ON                                                                            FOM Laser On                    Input                                         Asserting this signal HIGH enables Encode to                                  drive                                                                         LINK.sub.-- CONTROL output signal in either 10bit                             or 20bit mode.                                                   FDB.sub.-- OUT[19:0]                                                                       Fibre Data Out                  Output                                        These signals contain two 10-bit FCS characters                               that go to the                                                                FOM. See subsection entitled "Encode.sub.-- word                              Interface Formats"                                                            page 4-25 for the pin format.                                    PERROR       Parity Error                    Output                                        The Encode asserts this signal HIGH every time                                the Encode                                                                    detects a parity error on either one of the two                               8-bit characters just                                                         prior to being encoded to 10-bit.                     Arbitrated Loop                                                                          The Arbitrated Loop (AL) interface signals are grouped into                   following                                                          Signals    subsections:                                                                  ▪ Status                                                            ▪ Arbitration Control                                               ▪ Register Interface                                     Status     This group contains signals for indicating the operating                      status of the Arbitrated Loop.                                                STATUS.sub.-- REG9                                                                         Close state                     Output                                        Asserting this signal HIGH indicates that this                                port has                                                                      recognized a Close sequence on the loop.                         STATUS.sub.-- REG8                                                                         LIP Progress State              Output                                        Asserting this signal HIGH indicates that the                                 loop initialization                                                           is in progress.                                                  STATUS.sub.-- REG7                                                                         LIP Complete State              Output                                        Asserting this signal HIGH indicates that the                                 Loop initialization                                                           is complete.                                                     STATUS.sub.-- REG6                                                                         Opened State                    Output                                        Asserting this signal HIGH indicates that the                                 both initiator and                                                            target Loop ports are ready for communication.                   STATUS.sub.-- REG5                                                                         Open State                      Output                                        Asserting this signal HIGH indicates that this                                port is in Open                                                               state. This is the state during which a port                                  sends a primitive                                                             sequence to open another port for communication.                 STATUS.sub.-- REG4                                                                         Monitoring State                Output                                        Asserting this signal HIGH indicates that this                                port is in Monitoring                                                         state. In this state, Link is monitored                                       continuously for various                                                      Arbitrated Loop primitive sequences.                             STATUS.sub.-- REG3                                                                         Repetition State                Output                                        Assertion of this signal HIGH indicates that this                             port is in                                                                    Repetition state.                                                STATUS.sub.-- REG2                                                                         Arbitration in Progress for this                                                                              Output                                        Assertion of this signal indicates that this port                             is arbitrating for                                                            Loop.                                                            STATUS.sub.-- REG1                                                                         Arbitration in Progress for other                                                                             Output                                        Assertion of this signal indicates that some                                  other port is                                                                 arbitrating.                                                     STATUS.sub.-- REG0                                                                         No Operation                    Output                                        Loop is idle, LIP is complete and nothing is                                  happening on loop.                                    Arbitration Control                                                                      This group contains signals for Loop Arbitration.                             RQST.sub.-- ACC                                                                            Access Request                  Input                                         This signal is asserted HIGH by the downstream                                logic when a                                                                  communication is needed between this port and                                 another port.                                                    ACC.sub.-- GRANTED                                                                         Access Granted                  Output                                        This signal is asserted HIGH when arbitration is                              won by this                                                                   port.                                                 Register Interface                                                                       This group contains signals to interface AL registers to the                  downstream logic.                                                             AL.sub.-- REG{31:0]                                                                        Arbitrated Loop register Data Port                                                                            Input/Output                                  This is a bidirectional 32 bit port used to                                   access registers in AL.                                                       Data on this port is synchronous with T.sub.--                                WORD.sub.-- CLOCK.                                               AL.sub.-- RD.sub.-- WRITE                                                                  Arbitrated Loop Read Write Port                                                                               Inputol                                       Asserting this signal HIGH indicates a READ                                   operation and                                                                 deasserting this indicates WRITE operation for                                the selected                                                                  Register.                                                        AL.sub.-- REG.sub.-- SELECT{1:0]                                                           Arbitrated Loop register Select Input                                         These bits select one of the registers for                                    read/write operation.                                                         Bit[1:0]                                                                           Register                                                                 00   AL.sub.-- TMR.sub.-- REGISTER                                            01   PORT.sub.-- ACC.sub.-- REGISTER                                          10-11                                                                              Reserved                                                                 AL.sub.-- TMR.sub.-- REGISTER                                                 This is a 32 bit register used for loop time-out                              functions.                                                                    PORT.sub.-- ACC.sub.-- REGISTER                                               This is a 32 bit register and contains fiels for                              AL-PA(8bits) and                                                              status conditions(8bits) of other port.               Receive Signals                                                                          The Receive signals are grouped based on functional interface                 into the following subsections:                                               ▪ Receive Word Output                                               ▪ Steering                                                          ▪ Flow Control                                                      ▪ Frame Status                                                      ▪ R.sub.-- Status                                                   ▪ Control                                                           ▪ Register Interface                                     Receive Word Output                                                                      The Receive Word Output Interface provides the data output of                 the Receive Pipe. It includes word data                                       in 8-bit format, odd parity for each byte.                                    RECEIVE.sub.-- DOUT[35:0]                                                                  Receive Data Out                Output                                        These signals are the Receive Word Outputs, four                              parity                                                                        protected 8-bit characters per R.sub.-- word.sub.-                            - clk.                                                Steering   The NL.sub.-- Core supports two types of steering mechanisms,                 Steering.sub.-- Unmodified(SU) and Steering.sub.-- Class.sub.--                Header(SCH). This                                                            interface generates control signals to parse frame headers and                payload in to                                                                 their respective buffers. For SCH based steering, A Class1                    data frame is                                                                 parsed to send header to HC1 buffer and payload to pl.sub.--                  buffer. All Class1                                                            link frames go to HC1 buffer. For data frames in SCH steering,                header is                                                                     steered to hbb.sub.-- buffer and class 2/3 payload data is                    steered to pl.sub.-- buffer.                                                  However, link frames go to hbb.sub.-- buffer in entirety in                   Class2/3. In SU steering                                                      both data frames and link frames are directed to pl.sub.--                    buffer. However,                                                              custom steering is possible with control signals provided by                  the steering                                                                  logic. The number of different buffers and the size of each is                user-                                                                         definable.                                                                    The interface uses a 32-bit parity protected data interface                   RECEIVE.sub.-- DOUT[35:0] (four parity-protected bytes). The                  interface                                                                     includes three write strobes (two for header buffers and one                  for pl.sub.-- buffer),                                                        an end-of-frame signal, and a discard signal that discards                    unwanted frame                                                                headers after the write to the buffer is complete. All signals                come directly                                                                 from flip-flop outputs synchronous to the R.sub.-- WORD.sub.--                CLOCK.                                                                        FRAME.sub.-- DBA[31:0]                                                                     Frame Data Base Address         Output                                        These signals contain the starting buffer memory                              byte address                                                                  for the Payload Data in the current frame. Offset                             computation is                                                                performed (if used) irrespective of the type of                               steering selected.                                               EOF.sub.-- BIT                                                                             End of Frame                    Output                                        The Receive asserts this signal HIGH coincident                               with the last                                                                 word of frame. EOF delimiter is written if                                    encoded fromat if FIF                                                         is chosen.                                                       EOS.sub.-- BIT                                                                             End of Sequence                 Output                                        The Receive asserts this signal HIGH coincident                               with the EOF                                                                  of the last frame of a sequence, as determined by                             FHDR                                                                          F.sub.-- CTL19. This signal is used for steering                              the data after it leaves                                                      the core.                                                        DRIBBLE.sub.-- CNT[1:0]                                                                    Dribble byte count              Output                                        The Dribble Count is the number of fill bytes                                 that are in the last                                                          word of the frame. These signals reflect the FHDR                             F.sub.-- CTL[1:0]                                                             inputs. These signals are provided for FC-PH                                  service interface.                                               HC1.sub.-- DISCARD                                                                         Discard hc1.sub.-- buffer Entry Output                                        The Receive asserts this signal HIGH coincident                               with the last                                                                 word to be written to the pl.sub.-- buffer(s).                                When asserted HIGH, this                                                      signal prevents HIF.sub.-- LAST from forcing                                  buffer control to switch                                                      to the next buffer, since the current buffer is                               still free. This signal                                                       is used to cause the buffering mechanism to                                   discard the entire                                                            header entry it has just written.                                SOF.sub.-- HC1                                                                             Start of Frame to HC1 Buffer    Output                                        The Receive asserts this signal HIGH in                                       coincident with the SOF                                                       delimiter of a header write to HC1 buffer. This                               is applicable for                                                             both Data and Link Frames.                                       HC1.sub.-- WRITE                                                                           Write Word to hc1.sub.-- buffer Output                                        The Receive asserts this signal HIGH coincident                               with every                                                                    word that is to be written to the hc1.sub.--                                  buffer(s). It is active for                                                   Class1 headers (Data Frames) and Class1 link                                  frames except                                                                 SOFc1. This signal is used as a buffer write                                  pulse.                                                           SOF.sub.-- HBB                                                                             Start of Frame to HBB Buffer    Output                                        The Receive asserts this signal HIGH in                                       coincident with SOF                                                           delimiter for headers and Frames written to                                   hbb.sub.-- buffer.                                               HBB.sub.-- WRITE                                                                           Write Word to hbb.sub.-- buffer Output                                        The Receive asserts this signal HIGH coincident                               with every                                                                    word that is to be written to the hbb.sub.--                                  buffer(s). It is active on                                                    Class 2, Class 3 and SOFc1 frames. This signal is                             used as a                                                                     buffer write pulse.                                              SOPL.sub.-- C1                                                                             Start of Class1 Payload to PL.sub.-- Buffer                                                                   Output                                        The Receiver asserts this signal HIGH in                                      coincident with the first                                                     word of the payload to the buffer.                               SOPL.sub.-- BB                                                                             Start of BBFLO payload to PL.sub.-- Buffer                                                                    Output                                        The Receiver asserts this signal HIGH in                                      coincident with the first                                                     word of the payload to the buffer.                               PL.sub.-- WRITE                                                                            Write Word to PL.sub.-- Buffer  Output                                        The Receive asserts this signal HIGH coincident                               with every                                                                    word of Device Data for Class 1 frames and Class                              2/3 Frames.                                                                   This signal is used to initiate a write to a                                  pl.sub.-- buffer.                                                FD.sub.-- TYPE[3:0]                                                                        Data Type (Device, Video, or Link)                                                                            Output                                        These signals reflect FHDR R.sub.-- CTL[27:24]                                and can be used to                                                            differentiate between various frame data types,                               primarily for the                                                             purpose of steering the data after it leaves the                              core.                                                            CL.sub.-- TYPE[2:0]                                                                        Class Type                      Output                                        The Receive encodes these bit to show the Class                               type of the                                                                   Frame in reception.                                                           CL bit                                                                             Class Type                                                               00   Reserved                                                                 01   Class1                                                                   10   Class2                                                                   11   Class3                                           Flow Control                                                                             The Flow Control Interface provides a signal for                              hardware-managed R.sub.-- RDY flow control.                                   Flow control ensures receiver's buffer availability.                          R.sub.-- RDY R.sub.-- RDY Received           Output                                        The Receive asserts this signal HIGH for a clock                              cycle each time                                                               an R.sub.-- RDY is received in the Receive. This                              signal should be used                                                         to decrement the Credit Counter (C.sub.-- C) by                               connecting it to the                                                          R.sub.-- RDY.sub.-- RCVD input of the Transmit.       Frame Status                                                                             The Frame Status Interface provides an encoded description of                 parsed frames, indicating which portion                                       of the frame is currently active on Receive Word Output[35:0],                and any error conditions associated                                           with the frame.                                                               FRAME.sub.-- STATUS6                                                                       Frame Discard                   Output                                        This signal is asserted to specify that the                                   current frame can be                                                          discarded by the downstream logic. This signal is                             valid only                                                                    when the ENABLE.sub.-- FRAME.sub.-- DISCARD                                   control bit is set and is                                                     derived from various error status bits. NL.sub.--                             Core asserts this                                                             signal when there is a frame anomaly, CRC error                               or decode error.                                                 FRAME.sub.-- STATUS5                                                                       CRC Error                       Output                                        If a CRC error is detected, the NL.sub.-- Core                                asserts this signal HIGH                                                      coincident with the last frame word on Receive                                Word                                                                          Output[35:0].                                                    FRAME.sub.-- STATUS4                                                                       Decode Error                    Output                                        If a decode error is detected, The NL.sub.-- Core                             asserts this signal                                                           HIGH coincident with any word on Receive Word                                 Output[35:0].                                                    FRAME.sub.-- STATUS[3:0]                                                                   Frame Parsing Tags              Output                                        These signals are active concurrent with the                                  Receive Word                                                                  Output[35:0] data. These signals encode the frame                             status as follows:                                                            FRAME.sub.-- STATUS[3:0]                                                      ST.sub.-- IDLE                                                                        'h0                                                                              Not a frame word                                                   ST.sub.-- SOF                                                                         'h1                                                                              SOF word                                                           ST.sub.-- FHDR0                                                                       'h2                                                                              Frame Header 0 word                                                ST.sub.-- FHDR1                                                                       'h3                                                                              Frame Header 1 word                                                ST.sub.-- FHDR2                                                                       'h4                                                                              Frame Header 2 word                                                ST.sub.-- FHDR3                                                                       'h5                                                                              Frame Header 3 word                                                ST.sub.-- FHDR4                                                                       'h6                                                                              Frame Header 4 word                                                ST.sub.-- FHDR5                                                                       'h7                                                                              Frame Header 5 word                                                ST.sub.-- OHDR1                                                                       'h8                                                                              Optional Header 1 (Expiration) word                                ST.sub.-- OHDR2                                                                       'h9                                                                              Optional Header 2 (Network) word                                   ST.sub.-- OHDR3                                                                       'ha                                                                              Optional Header 3 (Association) word                               ST.sub.-- OHDR4                                                                       'hb                                                                              Optional Header 4 (Device) word                                    ST.sub.-- DATA                                                                        'hc                                                                              Frame Data word                                                    ST.sub.-- CRC                                                                         'hd                                                                              Frame CRC word                                                     ST.sub.-- FIF1                                                                        'he                                                                              Frame FIF1 word, if FIF is selected                                ST.sub.-- EOF                                                                         'hf                                                                              EOF word                                   R.sub.-- Status                                                                          The Status Interface is a group of outputs that flag various                  states and events of Receive section of                                       NL.sub.-- Core. States are active for the duration of the                     translation, where events are active for a single                             clock cycle and are meant to be captured elsewhere in the                     ASIC. All signals come directly from flip-                                    flop outputs synchronous to the R.sub.-- WORD.sub.-- CLOCK                    output.                                                                       STATUS.sub.-- REG10                                                                        Sequence Changed                Output                                        The Receive asserts this signal HIGH when a new                               Sequence                                                                      Frame is received during the current Sequence                                 reception.                                                       STATUS.sub.-- REG11                                                                        Exchange Changed                Output                                        The Receiver asserts this signal HIGH whenever                                RX.sub.-- ID                                                                  changes during the Exchange reception.                           STATUS.sub.-- REG9                                                                         Intermix Fault                  Output                                        The Receive asserts this signal HIGH if                                       CTRL.sub.-- REG5 is                                                           asserted HIGH and any Class 2/3 frame is                                      received. (Asserting                                                          CTRL.sub.-- REG5 selects the Non-intermix Mode.)                 STATUS.sub.-- REG8                                                                         Not Operational Sequence (NOS) Detected                                                                       Output                                        The Receive asserts this signal HIGH when                                     detecting a Not                                                               Operational Sequence State on FDB.sub.-- IN[19:0].                             (See Note on                                                                 page 3-13.)                                                      STATUS.sub.-- REG7                                                                         OLS Detected                    Output                                        The Receive asserts this signal HIGH when                                     detecting an Off-line                                                         Sequence State on FDB.sub.-- IN[19:0]. (See Note                              on page 3-13.)                                                   STATUS.sub.-- REG6                                                                         LRR Detected                    Output                                        The Receive asserts this signal HIGH when                                     detecting a Link                                                              Reset Response Sequence State on FDB.sub.--                                   IN[19:0]. (See Note on                                                        page 3-13.)                                                      STATUS.sub.-- REG5                                                                         LR Detected                     Output                                        The Receive asserts this signal HIGH when                                     detecting a Link                                                              Reset Sequence State on FDB.sub.-- IN[19:0]. (See                             Note on page 3-13.)                                              STATUS.sub.-- REG4                                                                         Sequence Error                  Output                                        The Receive asserts this signal HIGH when it                                  detects a sequence                                                            error. A sequence error occurs when the FHDR                                  SEQ.sub.-- CNT is not                                                         equal to the HMS.sub.-- SEQ.sub.-- CNT Internal                               Register for all classes, if                                                  CTRL.sub.-- REG8 is asserted HIGH.                                            If CTRL.sub.-- REG5 is deasserted LOW(Intermix                                selected),                                                                    Sequence Validity is not checked.                                STATUS.sub.-- REG3                                                                         Frame Interrupt Error           Output                                        The Receive asserts this signal HIGH to indicate                              that it detected                                                              a frame anomaly. A frame anomaly is caused by one                             of the                                                                        following events:                                                             (a) A SOF occurred before the previous frame                                  completed.                                                                    (b) An IDLE occurred before EOF was reached.                                  (c) An EOF occurred when there was not a frame in                             progress.                                                        STATUS.sub.-- REG2                                                                         Decode Error                    Output                                        The Receive asserts this signal HIGH when it                                  detects an error on                                                           the incoming 10-bit data.                                        STATUS.sub.-- REG1                                                                         CRC Error                       Output                                        The Receive asserts this signal HIGH when it                                  detects a frame                                                               CRC error.                                                       STATUS.sub.-- REG0                                                                         Sync Acquired                   Output                                        The Receive asserts this signal HIGH to indicate                              the core is in                                                                the Sync Acquired State as defined by the FCS.                                The Receive                                                                   deasserts this signal LOW to indicate that the                                Receive state                                                                 machine is in the Not Sync Acquired State as                                  defined by the                                                                FCS.                                                  Note:                                                                              This signal follows FCS rules by activating on detection of three             consecutive valid transmission words of this type.                            It deactivates on a single non-occurrence of a valid transmission             word of this type. The Link Control State                                     Machine can be implemented in either additional ASIC logic or in              software. The state machine should use a                                      capture-hold register to save this status.                               Control    The Control Interface is a group of inputs that are used to                   configure the Receive section of NL.sub.-- Core.                              All signals are assumed to be synchronous to the R.sub.--                     WORD.sub.-- CLOCK.                                                            CTRL.sub.-- REG6                                                                           Enable Sequence Validity Check  Input                                         Asserting this signal HIGH enables sequence                                   validity checking.                                                            It may be necessary to provide sequence validity                              for Intermix                                                                  operation provided the Fabric assures the                                     in-order delivery of                                                          frames in each class.                                            CTRL.sub.-- REG5                                                                           Enable Frame Interface Formats  Input                                         Asserting this signal HIGH enables encoding of                                the received                                                                  frame to Frame Interface Format.                                 CTRL.sub.-- REG4                                                                           Steering Select                 Input                                         Asserting this signal HIGH selects                                            Steering.sub.-- Unmodified, which                                             suppresses any attempt to modify incoming frames.                             Deasserting                                                                   this signal LOW selects class header based                                    steering.                                                        CTRL.sub.-- REG3                                                                           Non-Intermix Select             Input                                         Asserting this signal HIGH selects Non-intermix                               Mode.                                                                         Deasserting this signal LOW selects Intermix                                  Mode.                                                            CTRL.sub.-- REG2                                                                           Force Parity Error              Input                                         Asserting this signal HIGH forces the generated                               parity to be                                                                  false (even parity) in order to test downstream                               parity detectors.                                                             Both byte parity generators generate even parity                              instead of the                                                                default odd parity.                                              CTRL.sub.-- REG1                                                                           Enable Frame Discard            Input                                         Asserting this signal HIGH enables Frame discard                              status signal                                                                 (FRAME.sub.-- STATUS6).                                          CTRL.sub.-- REG0                                                                           On-line Enable                  Input                                         Asserting this signal HIGH puts Receive in the                                on-line state, as                                                             defined by the FCS. FC-2 level logic should                                   assert this signal                                                            after Link Initialization is performed.               Register Interface                                                                       The Register Interface is a 32-bit path used to write to the                  Base Address Register(BAR). For more                                          information on the BAR Register see the subsection entitled                   "Base Address Register", page 2-15.                                           BAR.sub.-- DATAIN[31:0]                                                                    BAR Register Data Inputs        Input                                         These signals are inputs to the BAR Register.                                 While                                                                         WRITE.sub.-- BAR is active. BAR.sub.-- DATAIN                                 must be synchronous                                                           with to the R.sub.-- WORD.sub.-- CLOCK.                          WRITE.sub.-- BAR                                                                           Base Address Register Write Strobe                                                                            Input                                         Asserting this signal HIGH initiates writing                                  BAR.sub.-- DATAIN[31:0] into the Base Address                                 Register. This                                                                signal must be synchronous to the R.sub.--                                    WORD.sub.-- CLOCK and should                                                  be asserted for at least one clock cycle. T           Transmit Signals                                                                         The Transmit signals are grouped by interface into the                        following subsections:                                                        Register Interface                                                            T.sub.-- Status                                                               Control                                                                       Transmit Steering                                                             Transmit Frame                                                                Flow Control                                                                  Primitive Sequence Transmission                                    Register Interface                                                                       This interface contains signals for writing into and reading                  from HMS.sub.-- CTL.sub.-- REG, HMS.sub.-- SEQ.sub.-- CNT,                    R.sub.-- R, C.sub.-- C and Credit Limit registers. For more                   information see subsection entitled "Hardware                                 Sequencing Parameters & Registers", page 2-19. All signals are                synchronous to T.sub.-- WORD.sub.-- CLOCK.                                    T.sub.-- REG.sub.-- PORT[31:0]                                                             Transmit Register Access Port   Input/Output                                  These port signals are common to all register                                 access and are                                                                synchronous to T.sub.-- WORD.sub.-- CLOCK                        T.sub.-- RD.sub.-- WRT.sub.-- CTL                                                          Transmit Register Read Write Control                                                                          Input                                         These signals control read and write operation to                             the selected                                                                  register. Asserting this signal HIGH selects read                             and a LOW                                                                     selects write operation.                                         T.sub.-- REG.sub.-- SELECT[2:0]                                                            Transmit Register Select        input                                         These bits select a particular register as                                    follows:                                                                      Bit[2:0]                                                                            Register Name                                                           000   HMS.sub.-- CTL.sub.-- REGISTER                                          001   HMS.sub.-- SEQ.sub.-- CNT                                               010   R.sub.-- R                                                              011   C.sub.-- C                                                              100   Transmit Credit Limit                                                   101-111                                                                             None Selected                                                           HMS.sub.-- CTL.sub.-- REGISTER                                                This is a 32 bit register used to control                                     Hardware Managed                                                              Sequence implementation.                                                      HMS.sub.-- SEQ.sub.-- CNT                                                     This is a 16 bit register which holds the final                               sequence count                                                                (plus one) after a sequence transmission is                                   complete. This value                                                          can be used in the initial frame header of a                                  subsequent sequence,                                                          if that sequence is a continuation of a prior,                                non-contiguous                                                                sequence.                                                                     R.sub.-- R Counter                                                            This is a 8 bit counter register and the Transmit                             uses these signals                                                            to keep a count of the number of R.sub.-- RDY                                 Primitive Signals yet                                                         to be transmitted. The count ranges from 0x0 to                               0xFF.                                                                         C.sub.-- C Counter                                                            This is a 8 bit counter register and the Transmit                             uses these signals                                                            to keep the current credit count at the                                       destination link receiver.                                                    The count ranges from 0x0 to 0xFF.                                            Transmit Credit Limit                                                         This is a 8 bit counter register which is                                     programmed using login                                                        parameters to set credit limit.                       T.sub.-- Status                                                                          The Status Interface is a group of outputs that flag various                  Transmit states and events. States are                                        active for the duration of the state transition, where events                 are active for a single clock cycle and are meant                             to be captured elsewhere outside this core. All signals come                  directly from flip-flop outputs synchronous to the                            T.sub.-- WORD.sub.-- CLOCK.                                                   STATUS.sub.-- REG1                                                                         HMS Complete                    Output                                        The Transmit asserts this signal HIGH to flag                                 when the Transmit                                                             engine transmits EOF of the last frame.                          STATUS.sub.-- REG0                                                                         HMS Busy                        Output                                        The Transmit asserts this signal HIGH from the                                time the                                                                      HMS.sub.-- CTL.sub.-- REG is written until the                                Transmit engine has                                                           transmitted EOF of the last frame of the                                      sequence.                                             Control    The Control Interface is a group of inputs that are used to                   configure the Transmit. All signals are assumed                               to be synchronous to the Transmit Clock.                                      CTRL.sub.-- REG2                                                                           Flow Control Reset              Input                                         Asserting this signal HIGH resets the R.sub.-- R                              and the C.sub.-- C.                                              CTRL.sub.-- REG1                                                                           Force CRC Error                 Input                                         Asserting this signal HIGH forces CRC errors. For                             as long as                                                                    this signal is asserted HIGH, the Transmit forces                             incorrect CRC                                                                 on all frames transmitted, which causes the                                   destination link                                                              receiver to detect and report this type of error.                CTRL.sub.-- REG0                                                                           Force 10-Bit Decode Error       Input                                         Asserting this signal HIGH forces a 10-bit decode                             error. When                                                                   this signal is HIGH, the Transmit outputs IDLEs                               with incorrect                                                                disparity, which causes the destination link                                  receiver to detect and                                                        report this type of error.                            Transmit Steering                                                                        This group contains signals to provide handshake mechanism                    with external buffers.                                                        XMIT.sub.-- BUSY                                                                           Transmit Busy                   Output                                        This signal is asserted HIGH during the period                                from SOF to EOF                                                               of any frame transmission.                                       PL.sub.-- RD Read enable for PL.sub.-- buffer                                                                              Output                                        This signal is asserted HIGH when the Transmit                                decides to read                                                               a word from PL.sub.-- buffer.                                    PL.sub.-- RDY                                                                              Frame Payload Ready to Transmit Input                                         This signal is asserted HIGH when the payload is                              ready to be                                                                   transmitted in the downstream logic. Transmit                                 uses PL.sub.-- RDY                                                            and XMIT.sub.-- BUSY to control PL.sub.-- RD                                  generation.                                                      PL.sub.-- FIRST                                                                            Payload First Word indicator    Output                                        This signal is asserted during the period when                                the first word of                                                             the payload is being read into the transmit.                     PL.sub.-- LAST                                                                             Payload Last Word indicator     Input                                         This signal is asserted HIGH by the external                                  logic to indicate the                                                         last word transfer of the payload.                               LINK.sub.-- CTL.sub.-- RD                                                                  Link Control Frame Read Enable  Output                                        This signal is asserted HIGH when the Transmit                                decides to read                                                               a word of Link Control Frame.                                    LINK.sub.-- CTL.sub.-- RDY                                                                 Link Control Frame Ready        Input                                         This signal is asserted HIGH by the downstream                                logic to indicate                                                             the availability of Link Control Frames.                         LINK.sub.-- CTL.sub.-- FIRST                                                               Link Control Frame First Word indicator                                                                       Output                                        This signal is asserted HIGH during the period                                when the first                                                                word of Link Control Frame is being transmitted.                 LINK.sub.-- CTL.sub.-- LAST                                                                Link Control Frame Last Word indicator                                                                        Input                                         This signal is asserted HIGH by the external                                  logic indicate the                                                            last word of a Link Control Frame.                               HC1.sub.-- RD                                                                              Class1 Buffer Read Enable       Output                                        This signal is asserted HIGH when the Transmit                                decides to read                                                               a word from HC1 buffer.                                          HC1.sub.-- RDY                                                                             Class1 Header Ready             Input                                         This signal is asserted HIGH to indicate the                                  availability of                                                               Class1 header.                                                   HC1.sub.-- FIRST                                                                           Class1 Header First Word indicator                                                                            Output                                        This signal is asserted HIGH during the period                                when the first                                                                word of a Class1 frame header is being read.                     HC1.sub.-- LAST                                                                            Class1 Header Last Word indicator                                                                             Input                                         This signal is asserted HIGH by the external                                  logic to indicate the                                                         last word transfer of Class1 header.                             HBB.sub.-- RD                                                                              hbb.sub.-- buffer Read Enable   Output                                        This signal is asserted HIGH when the transmit                                decides to read                                                               a word from HBB buffer.                                          HBB.sub.-- RDY                                                                             BBFLO Frame Ready               Input                                         This signal is asserted HIGH to indicate the                                  availability of                                                               BBFLO frame.                                                     HBB.sub.-- FIRST                                                                           BBFLO Frame First Word          Output                                        This signal is asserted HIGH during the period                                when the first                                                                word from a hbb.sub.-- buffer is being                                        transmitted.                                                     HBB.sub.-- LAST                                                                            BBFLO Frame Last Word           Input                                         This signal is asserted HIGH by the external                                  logic to indicate the                                                         last word transfer of a hbb.sub.-- buffer.            Transmit Frame                                                                           This group contains signals for datapaths for Payload, Link                   Control, HC1 and HBB word datum.                                              PL.sub.-- D[35:0]                                                                          Payload Data Bus                Input                                         This is a 32 bit parity protected data path for                               the payload.                                                     LINK.sub.-- CTL.sub.-- D[35:0]                                                             Link Control Frame Data Bus     Input                                         This is a 32 bit parity protected data path for                               Link Control                                                                  Frames.                                                          HC1.sub.-- D[35:0]                                                                         Class1 Header Data Bus          Input                                         This is a 32 bit parity protected data path for                               Class1 headers.                                                  HBB.sub.-- D[35:0]                                                                         BBFLO Frame Data Bus            Input                                         This is a 32 bit parity protected data path for                               BBFLO headers.                                        Flow Control                                                                             The Flow Control Interface provides signals for managing                      R.sub.-- RDY flow control mechanisms in the Transmit.                         INCREMENT.sub.-- RRDY                                                                      Increment R.sub.-- R Counter    Input                                         Asserting this signal HIGH increments the                                     R.sub.-- R Counter. This                                                      event should occur once every time the NL.sub.--                              Port's BBFLO input                                                            buffer is emptied of an entry. Since the event                                probably originates                                                           in a different clock domain, this input feeds a                               resynchronization                                                             signal and a one-shot, thus incrementing the                                  R.sub.-- R Counter once                                                       per high-going edge.                                             RRDY.sub.-- RCVD                                                                           Decrement C.sub.-- C            Input                                         Asserting this signal HIGH decrements the                                     C.sub.-- C by one. This                                                       signal should be asserted every time the Receive                              in the same                                                                   NL.sub.-- Port receives an R.sub.-- RDY Primitive                             Signal (it is meant to be                                                     connected to the Receive R.sub.-- RDY output                                  pin). This input feeds                                                        a resynchronization and one-shot, thus                                        decrementing the C.sub.-- C                                                   once per high-going edge.                             Primitive Sequence                                                                       These signals enable the Transmit to transmit Primitive                       Signals and Sequences (Continuous Ordered Sets) on                 Transmission                                                                             FDB.sub.-- OUT[19:0] as follows:                                              IDLE         Idle Primitive Signal Enable    Input                                         Asserting this signal HIGH enable Transmit to                                 schedule an                                                                   IDLE primitive signal transmission.                              R.sub.-- RDY R.sub.-- RDY Primitive Signal Enable                                                                          Input                                         Asserting this signal HIGH enables Transmit to                                schedule a                                                                    R.sub.-- RDY primitive signal transmission.                      NOS          Not Operational Primitive Sequence                                                                            Inpute                                        Asserting this signal HIGH enables Transmit to                                schedule a NOS                                                                primitive sequence for transmission.                             OLS          Off-line Enable                 Input                                         Asserting this signal HIGH enables Transmit to                                schedule a OLS                                                                primitive sequence for transmission.                             LRR          Link Reset Response Enable      Input                                         Asserting this signal HIGH enables Transmit to                                schedule a LRR                                                                primitive sequence for transmission.                             LR           Link Reset                      Input                                         Asserting this signal HIGH enables Transmit to                                schedule a LR                                                                 primitive sequence for transmission.                  3.6 Miscellaneous                                                                        This group contains signals for test, clock generation and                    reset operation.                                                   Signals                                                                       Test and Scan                                                                            The Test and Scan Interface controls the scan test mechanism                  that is used for ASIC production tests.                                       TAI          Asynchronous Clear Enable       Input                                         Asserting this signal HIGH disables all flip-flop                             asynchronous                                                                  sets or resets during the scan process.                          TMOD         Test Mode                       Input                                         Asserting this signal HIGH puts all flip-flops in                             the test mode for                                                             scan.                                                            TSDI         Scan Data In                    Input                                         This signal feeds the first flip-flop of the scan                             chain.                                                           TSDO         Scan Data Out                   Output                                        This signal is fed by the last flip-flop of the                               scan chain.                                           Clock Out  The Clock Out Interface feeds condition versions of the source                clock to external circuits.                                                   R.sub.-- WORD.sub.-- CLK                                                                   Receive Word Clock              Output                                        This word clock is derived from R.sub.-- CLK.                                 R.sub.-- CLK divided by                                                       two drives this output for 20 bit mode and                                    R.sub.-- CLK divided by                                                       four in 10bit mode.                                              T.sub.-- WORD.sub.-- CLK                                                                   Transmit Word Clock             Output                                        This word clock is derived from T.sub.-- CLK.                    T.sub.-- CLK.sub.-- OUT                                                                    Copy of the T.sub.-- CLK Clock input                                                                          Output                                        This is a buffered version of T.sub.-- CLK and                                may be used elsewhere.                                           R.sub.-- CLK.sub.-- OUT                                                                    Copy of the R.sub.-- CLK Clock input                                                                          Output                                        This is a buffered version of R.sub.-- CLK and                                may be used elsewhere.                                TClock In  Clock In Interface takes clock sources from FOM modules.                      R.sub.-- CLK Receiver Recovered Clock        Input                                         The FOM byte clock inputs this signal. It should                              cycle once                                                                    every two 10-bit characters if in 20-bit mode, or                             once every one                                                                10-bit character in 10-bit mode. This clock must                              have one of the                                                               following nominal frequencies ± 100 PPM:                                   FCS Speed                                                                            Frequency (in MHz)                                                     Full   53.125                                                                 Half   26.5625                                                                Quarter                                                                              13.28125                                                               Eighth 6.640625                                                  T.sub.-- CLK Transmitter Clock               Input                                         The FOM byte clock inputs this signal. It should                              cycle once                                                                    every two 10-bit characters if in 20-bit mode, or                             once every one                                                                10-bit character in 10-bit mode. This clock must                              have one of the                                                               following nominal frequencies ± 100 PPM:                                   FCS Speed                                                                            Frequency (in MHz)                                                     Full   53.125                                                                 Half   26.5625                                                                Quarter                                                                              13.28125                                                               Eighth 6.640625                                                  NL.sub.-- RESET                                                                            Assertion of this signal puts all the sequential                              elements in the                 Input                                         NL.sub.-- Core in its reset state.                    __________________________________________________________________________

Disclosed now are the core operation and formats, including Core Setup,Arbitrated Loop Programming, Receive Programming, Transmit Programming,and Frame Interface Formats (FIF).

Core Setup

Following is a description of the steps necessary for setting up theNode Loop core.

    __________________________________________________________________________                     Power on Reset value for all the registers is zero.                           1.                                                                              Reset the Node Loop core. Assert Reset signal LOW for                         at least 4                                                                    clock cycles.                                                                   Arbitrated Loop: NL.sub.-- Core reset resets                                  arbitrated loop circuitry.                                                    The loop set up is completed when the loop                                    initialization protocol                                                       is complete, which initializes the AL.sub.-- PA                               (arbitrated loop physical                                                     address).                                                                     Receive                                                                       While CTRL.sub.-- REG2 is asserted, program the FOM                           Type signal,                                                                  CTRL.sub.-- REG[1:0], the Input Character Select                              signal,                                                                       CTRL.sub.-- REG4, the Intermix Select signal,                                 CTRL.sub.-- REG5, and the                                                     Steering Select signal, CTRL.sub.-- REG6. For more                            information on                                                                these signals, see the subsection entitled "Control"                          on page 3-13.                                                                 Transmit                                                                      While Reset is asserted LOW, program the FOM Type                             signal,                                                                       CTRL.sub.-- REG6. For more information on this                                signal, see the                                                               subsection entitled "Control" on page 3-17.                                 Deassert the reset signals.                                                 2.                                                                              Set up buffer-to-buffer flow parameters for the                               Transmit.                                                                     Load the number of buffers available (acquired at                             login) into the Credit                                                        Limit signals, CTRL.sub.-- REG[15:12]. For more                               information on these                                                          signals, see the subsection entitled "Control" on page                        3-17.                                                                       3.                                                                              Program the Base Address Register (BAR) for the                               Receive operation                                                             if Offset is used. At power on, the register value is                         0, therefore it needs                                                         to be programmed by downstream logic before it is                             used.                                                                         Load the base address into base address                                       register[31:0], and then pulse                                                the BAR with Write.sub.-- BAR strobe, synchronous to                          the R.sub.-- word.sub.-- clk                                                  clock.                                                                        For more information on the Base Address Register see                         the subsection                                                                entitled "Register Interface" on page 3-14 and the                            subsection entitled                                                           "Base Address Register" on page 2-15.                      Arbitrated Loop Programming                                                                    Once NL.sub.-- Core is set up, the arbitrated loop                            operates on-line.                                                             "Core Setup" describes NL.sub.-- Core setup.                                  Whenever loop access is required REQUEST.sub.-- ACCESS                        is asserted by the                                                            downstream logic. Loop State Machine (LSM) checks if                          nobody using                                                                  loop, if so, LSM initiate ARBx, where x is AL.sub.-- PA.                      LSM waits until ARBx                                                          comes back through loop, then LSM goes into                                   Arbitration.sub.-- won state and                                              will try to open required port for unidirectional or                          bidirectional data                                                            transfers. At the end of the data transfers, NL.sub.--                        Port transmits a close sequence                                               (CLS). If loop is being used by any other two ports,                          NL.sub.-- Port waits (is in                                                   monitoring and repetition state) to observe CLS from                          both the ports, before                                                        ARBx is transmitted on the loop. After the arbitration                        is won and the other                                                          port is OPENED, arbitrated loop engine sets                                   ACCESS.sub.-- GRANTED for the                                                 downstream logic. With the reception of ACCESS.sub.--                         GRANTED signal,                                                               receive and transmit engines are in OPERATION STATE.         Receive Programming                                                                            Once NL.sub.-- Core is set up, the Receive operates                           on-line. Section 4.1, "Core                                                   Setup" describes NL.sub.-- Core setup.                                        FIGS. 10A-10C show the Receive operating algorithm. As                        described by FCS,                                                             the receive engine asserts synchronization.sub.--                             acquired, after receiving the                                                 three consecutive valid words. Then link initialization                       protocol is                                                                   followed. At the successful completion of Link                                Initialization Protocol, the                                                  NL.sub.-- Port is in active state, and it expects idle,                       R.sub.-- RDY, or SOF delimiter                                                for a frame. If the port receives primitive sequence,                         then it exists active state                                                   and enters one of the link states.                                            When SOF is detected, the frame is steered on the basis                       of steering                                                                   mechanism programmed (refer to CTRL.sub.-- REG).                              Sequence validity is checked,                                                 if CTRL.sub.-- REG is asserted. Base address for each                         frame is computed, if the                                                     offset is used (CTRL.sub.-- REG), and the WRITE.sub.--                        BAR is performed prior to                                                     receiving the first frame of a sequence.                     Functional Waveforms                                                                           FIG. 11A shows the reception of class 1 frames, when                          steering.sub.-- unmodified is selected. FD.sub.-- TYPE                        provides the frame data type,                                                 CL.sub.-- TYPE provides class of service, FRAME.sub.--                        STATUS provides the                                                           frame parsing tags, SOF and EOF are also provided by the                      Receive                                                                       Engine. All these signals may be used for custom                              steering implementation.                                                      Similarly, FIG. 11B shows the reception of class 2/3                          frames, when                                                                  steering.sub.-- unmodified is selected.                                       FIG. 11C shows the reception of class 2/3 data frames,                        when                                                                          steering.sub.-- header.sub.-- class is selected. The                          header is steered to hbb.sub.-- buffer, and                                   the payload data to pl.sub.-- buffer. FIG. 11D shows the                      reception of class 1 data                                                     frames, when steering.sub.-- header.sub.-- class is                           selected. The header is steered to                                            hc1.sub.-- buffer, and the payload data to pl.sub.--                          buffer.                                                      Word Synchronization                                                                           FIG. 12 shows the Receive Word Synchronization State                          Machine                                                                       diagram. The tables below describe the Receive states                         and show the                                                                  Receive state transition conditions.                                          A transmission character is any encoded character (valid                      or invalid)                                                                   transmitted across a physical interface specified by                          FC-0. Valid Transmission                                                      Characters are specified by the Transmission Code and                         include Data and                                                              Special Characters.                                                           A transmission word is a string of four contiguous                            Transmission                                                                  Characters occurring on boundaries that are zero modulo                       four from a previously                                                        received Primitive Sequence.                                                  An ordered set is a transmission word composed of a                           K28.5 Character in                                                            its first byte followed by three Data Characters.                             When three valid ordered sets are received, the word                          synchronization is                                                            achieved. This state is A in FIG. 12.                        Receive State Descriptions                                                                     State                                                                             Description (Detection State)                                             A   No Invalid Transmission Word                                              B   First Invalid Transmission Word                                           C   Second Invalid Transmission Word                                          D   Third Invalid Transmission Word                                           E   Fourth Invalid Transmission Word                                              (Loss of Synchronization)                                                 F   Reset                                                    Receive State Transition                                                                       State                                                        Conditions       Transition                                                                           Transition Condition                                                   a      The first invalid transmission word is detected                        b      An additional invalid transmission word is not                                detected in the                                                               next two or fewer consecutive transmission words                       c      An additional invalid transmission word is                                    detected in the next                                                          two or fewer consecutive transmission words                            d      The receiver detects three ordered sets, not                                  necessarily consecutive,                                                      without any intervening error conditions                               e      The receiver is reset                                                  f      The receiver exits a previously established reset                             condition                                                              g      Loss of signal                                        Transmit Programming                                                                           Following is a description of how to use the Transmit.                        FIGS. 13A-                                                                    13B show the Transmit operating algorithm. At the                             successful completion                                                         of Link Initialization Protocol, the NL.sub.-- Port is                        in active state, and                                                          the transmit is on-line. If there are any outstanding                         R.sub.-- RDYs to be sent                                                      (R.sub.-- R counter value is not equal to zero),                              R.sub.-- RDY preceded and followed                                            by two idle primitive signals will be transmitted. Of                         the multiple frame                                                            sources, link frames have the highest priority,                               therefore, if a link frame is                                                 ready to be transmitted, then transmit engine sends link                      frame first. All the                                                          single data frames are expected from the generic path                         that is pl.sub.-- buffer or                                                   Data.sub.-- FIFO (transmit). The hardware managed                             sequence for class 1 service                                                  uses hardware to transmit SOF and header, hc1.sub.--                          buffer to transmit optional                                                   headers (if present), pl.sub.-- buffer to transmit                            payload data, and hardware to                                                 transmit CRC and EOF. For class 2/3 HMS transmit, there                       are two basic                                                                 differences, one is transmit engine reads optional                            header (if present) from                                                      hbb.sub.-- buffer, and the second difference is that the                      transmit checks the C.sub.-- C                                                counter value to ensure the remote receiver is ready.                         BBFLO flow control rules are applied to Class 1 SOFc and                      all Class 2 and                                                               3 frame transmissions.                                       Functional Waveforms                                                                           FIG. 14A shows the functional waveforms to transmit a                         single frame. The                                                             frame is read off the payload buffer. FIG. 14B shows the                      functional wave-                                                              form of transmitting a link frame. This path is used for                      transmitting ACK                                                              and other link control frames.                               __________________________________________________________________________

FIG. 14C shows the transmission of HMS frame when optional headers arepresent. For this frame, header is prepared by hardware, optionalheaders are read from hcl₋₋ buffer or hbb₋₋ buffer, payload are readfrom pl₋₋ buffer, CRC and EOF are prepared by hardware. FIG. 14D showsback to back frame transmission of HMS, when optional headers are notpresent.

    __________________________________________________________________________    BB Flow Control  FIG. 15 shows the R.sub.-- RDY flow control mechanism.                        Initial credit                                                                count (C.sub.-- C counter) and R.sub.-- RDY buffer count                      (R.sub.-- R counter) are loaded                                               by the credit counts determined during login. When ever                       a BB Flow frame                                                               is transmitted, C.sub.-- C counter is decremented and                         R.sub.-- RDY received C.sub.-- C                                              counter is incremented. When the local buffer is                              released, Increment                                                           R.sub.-- RDY signal is received, which in turn                                increments R.sub.-- R counter. When                                           an R.sub.-- RDY is transmitted, the R.sub.-- R counter                        is decremented.                                                               R.sub.-- RDY primitives are preceded and followed by a                        minimum of two                                                                IDLEs. All frames are separated by a minimum of six                           primitive signals.                                           Transmit State Diagram                                                                         Transmit always in working state or reset state, as                           described in FCS. In                                                          working state, transmit may be in Link initialization                         state (one of the link                                                        states NOS, OLS, LR, LRR), primitive signal state                             (transmitting idle or                                                         R.sub.-- RDY), or frame.sub.-- transmit state.               Transmitting a Single FCS Frame                                                                To transmit a single frame, write the frame in entirety                       to pl.sub.-- buffer and                                                       assert pl.sub.-- rdy signal. When Transmit asserts                            pl.sub.-- read.sub.-- first and pl.sub.-- read, for                           each T.sub.-- WORD.sub.-- CLK negative to positive going                      edge one word is read                                                         from the payload buffer. External logic asserts                               pl.sub.-- last for the last data word                                         of the frame, then pl.sub.-- read is deasserted by                            transmit engine. CRC is                                                       generated by hardware and transmitted preceding the EOF                       delimiter.                                                   Transmitting a Hardware-                                                                       The Hardware Managed Sequence (HMS) Frame Header                              Mechanism                                                    Managed Sequence contains the bytes for the SOF, FHDR and (optionally)                         OHDR fields. If                                                               OHDRs are not used, the Transmit prepares the header and                      transmits. For                                                                the first frame of HMS, the header is read from buffer,                       and it is stored in                                                           the h.sub.-- wd0.sub.-- reg to h.sub.-- wd6.sub.-- reg.                       For subsequent intermediate frames these                                      registers are used to transmit frame header. For the                          last frame of sequence,                                                       header words storage registers and hms.sub.-- ctl                             register are used to transmit                                                 frame header. If OHDRs are used, the Transmit sends the                       header and                                                                    optional header is read out of header buffer (either HC1                      for class 1                                                                   sequence, HBB for class 2/3 data frames). The FHDR                            DF.sub.-- CTL field                                                           indicates which optional headers are in use.                                  The HMS header should only be programmed with SOFi1,                          SOFn1, SOFi2,                                                                 SOFn2, SOFi3 and SOFn3 codes with FHDR                                        R.sub.-- CTL[31:28] = 0xxx.sub.2                                              (Device Data or Video Data frames).                                           If the HMS header is programmed for Class 2 or 3, the                         HMS must be                                                                   programmed so that frames are not generated longer than                       the minimum of                                                                either the BBFLO buffer size in the fabric or in the                          destination link receiver.                                                    To transmit a Hardware-Managed Sequence, write the                            header of the first                                                           frame to hbb.sub.-- buffer if class 2/3 service is used                       or to hc1.sub.-- buffer if class 1                                            service is used. Program hms.sub.-- ctl register. Write                       hms.sub.-- seq.sub.-- cnt register if                                         the sequence count (SEQ.sub.-- CNT) of the first frame                        of the sequence is other                                                      than zero or not equal to the last frame SEQ.sub.-- CNT                       +1 of the previous                                                            hardware managed sequence.                                                    For class 2/3 service, maximum payload size during the                        login has to be                                                               programmed.                                                                   When the Transmit is ready to begin transmitting, it                          asserts HC1.sub.-- RD to                                                      read from HC1 buffer, HBB.sub.-- RD to read from HBB                          buffer, PL.sub.-- RD to read                                                  from the payload buffer, and LINK.sub.-- CTL.sub.-- RD                        for link frames. The Transmit                                                 now expects data to be available on the next clock cycle                      and every The                                                                 Transmit increments the Sequence Count automatically and                      inserts the                                                                   value into the frame header.                                 Transmitting a Primitive Sequence                                                              To transmit a Primitive Sequence, first set the                               appropriate Transmit                                                          Primitive Transmission Control signals, CTRL.sub.--                           REG[5:0].                                                                     The Transmit engine begins transmitting the Primitive                         Sequence as                                                                   soon as it has completed any frame transmission already                       in progress.                                                                  The Transmit continues to transmit the Primitive                              Sequence until                                                                CTRL.sub.-- REG[5:10] is reset to 000000.sub.2.              Transmitting an R.sub.-- RDY                                                                   Asserting INCREMENT.sub.-- RRDY increments the number of                      outstanding                                                  Primitive Ordered Set                                                                          R.sub.-- RDY's to be transmitted. R.sub.-- RDY                                primitives are preceded and followed                                          by a minimum of two IDLEs.                                   Frame Interface Formats (FIF)                                                                  The following sections describe the frame interface                           formats used in                                                               NL.sub.-- Core. Frame interface formats can be selected                       or deselected using                                                           control bits.                                                Receive FIF      In a receive, SOF and EOF are compacted into single                           bytes, freeing room                                                           for other data used to delineate and control the frame.                       FIG. 17 illustrates the Receive FIF. The Receive engine                       converts data                                                                 from FCS Format to FIF as it writes the data into either                      the BBFLO                                                                     (hbb.sub.-- buffer) or non-BBFLO (hc1) buffers.              Transmit FIF     This format is used for all frames input to the                               Transmit. It allows a                                                         Fibre Channel frame to exist outside the core without                         the use of 10-bit                                                             special characters to delineate frame start and end. SOF                      and EOF are                                                                   compacted to single bytes, freeing room for other data                        used to delineate                                                             and to control the frame.                                                     FIG. 18 illustrates the Transmit FIF. The Transmit                            coverts data from                                                             FIF to FCS format prior to transmitting.                     __________________________________________________________________________

While the invention has been described with reference to a specificembodiment, the description is illustrative of the invention and is notto be construed as limiting the invention. Various modifications andapplications may occur to those skilled in the art without departingfrom the true spirit and scope of the invention as defined by theappended claims.

What is claimed is:
 1. A node loop port core for use in a high speeddata system such as Fibre Channel for encoding, decoding and errorcontrol of transmitted data, said node loop port core comprising:adecode unit for receiving and decoding data including converting datawidth with error checking and constructing parity protected words fromhalfwords and bytes, an encode unit for encoding data for transmissionincluding converting data width and generating encoded halfwords orbytes after checking parity, a receive unit coupled with said decodeunit for forwarding data to a host interface after frame parsing, framesteering and error checking, a transmit unit coupled with said encodeunit for frame construction, CRC generation, Fibre Channel primitivesignal and sequence generation, and an arbitrated loop coupled to saiddecode unit, said encode unit, said receive unit, and said transmitunit, said arbitrated loop unit performing all arbitration functionsincluding recognition of primitive signals and sequences pertinent tosaid loop, said arbitrated loop including:a loop state machine forperforming loop initialization protocol, loop arbitration and loopfairness in accordance with Fibre Channel specifications, a firstmultiplexer controlled by said loop state machine for receiving andtransmitting decoded data from said decode unit, a second multiplexercontrolled by said loop state machine for receiving and transmittingdata from said transmit unit for port to port communication, and a loopbuffer connected with said loop state machine for receiving and retimingreceived words.
 2. The node loop port core as defined by claim 1 whereinsaid decode unit includes:a 20 bit input for use when a 20 bit mode isenabled, a 10 bit input for use when a 10 bit mode is enabled, a 10 bitdecoder coupled to said inputs and including two parallel 10 bit to 8bit decoders with error checking, a parity generator coupled to saiddecoder for receiving decoded data and generating and appending oddparity, a word assembler coupled to said parity generator for assembling32 bit parity protected data for said arbitrated loop, and a receiveword controller for receiving control signals and generating statussignals and controlling operations in said decode unit.
 3. The node loopport core as defined by claim 1 wherein said encode unit includes:a 20bit output for use when a 20 bit mode is enabled, a 10 bit output foruse when a 10 bit mode is enabled, an 8 bit encoder coupled to saidoutputs and including two parallel 8 bit to 10 bit encoders, a paritychecker coupled to said encoder and checking off parity and stripping aparity bit, a word disassembler coupled to said parity checker fordisassembling 32 bit parity protected data into 16 bit parity protecteddata for said parity checker and encoder, and a transmit word controllerfor receiving control signals and generating status signals andcontrolling operations in said encode unit.
 4. The node loop port coreas defined by claim 1 wherein said receive unit includes:a detectordered set unit for receiving decoded words from said decode unit anddetecting primitive signals, primitive sequences, and frame delimiters,a receive pipeline for recovery decoded words from said decode unit, aCRC unit for generating CRC bits for incoming frames from said receivepipeline and checking for correct CRC bits, a multiplexer for recoveringdata from said receive pipeline for transmission downstream, a steeringcontrol unit for providing logic signals for frame parsing and steering,a frame interface formats (FIF) converter for converting Fibre ChannelStandard format to FIF format, a frame control unit for providing frameparsing information for use in custom steering, a base address registerfor providing a base address for vectoring frames to a memory, and areceive control unit coupled to and controlling all other units of saidreceive unit, and providing all required status signals to downstreamlogic.
 5. The node loop port core as defined by claim 1 wherein saidtransmit unit includesa header multiplexer for multiplexing frameheaders from multiple sources, a frame data multiplexer unit connectedto said header multiplexer and receiving payload and link inputs andmultiplexing data and headers of frames, a CRC generate unit connectedto receive outputs from said frame data multiplexer and generating a CRCfor frames, an output multiplexer connected to receive outputs from saidCRC generate unit and including data paths for header and data, forstart of frame SOF and end of frame EOF delimiters, and CRC, said outputmultiplexer presenting transmission words to said encoder through saidarbitrated loop, a hardware sequencing parameters and registers unit forproviding necessary parameters for hardware managed sequences to saidheader multiplexer, a unit for performing primitive signal, sequence,and delimiter generation, a flow control unit for hardware managed flowcontrol and responsive to a R₋₋ RDY (receive unit ready) signals from aremote link receiver, and a transmit control unit interconnected withand controlling all units in a transmit operation including singleframes from said frame data multiplexer unit, sequences of frames in ahardware managed sequencing, idles and primitive sequences, buffer tobuffer flow control, frame delimiter generation, offset generation, andCRC generation and transmission for end of frame transmission.
 6. A nodeloop port core for use in a high speed data system such as Fibre Channelfor encoding, decoding and error control of transmitted data, said nodeloop port core comprising:a) a decode unit for receiving and decodingdata including converting data width with error checking andconstricting parity protected words from halfwords and bytes, saiddecode unit including:a 20 bit input for use when a 20 bit mode isenabled, a 10 bit input for use when a 10 bit mode is enabled, a 10 bitdecoder coupled to said inputs and including two parallel 10 bit to 8bit decoders with error checking, a parity generator coupled to saiddecoder for receiving decoded data and generating and appending oddparity, a word assembler coupled to said parity generator for assembling32 bit parity protected data for said arbitrated loop, and a receiveword controller for receiving control signals and generating controlsignals and controlling operations in said decode unit; b) an encodeunit for encoding data for transmission including converting data widthand generating encoded half-words or bytes after checking parity, saidencode unit including:a 20 bit output for use when a 20 bit mode isenabled, a 10 bit output for use when a 10 bit mode is enabled, an 8 bitencoder coupled to said outputs and including two parallel 8 bit to 10bit encoders, a parity checker coupled to said encoder and checking offparity and stripping a parity bit, a word disassembler coupled to saidparity checker for disassembling 32 bit parity protected data into 16bit parity protected data for said parity checker and encoder, and atransmit word controller for receiving control signals and generatingstatus signals and controlling operations in said encode unit; c) areceive unit coupled with said decode unit for forwarding data to a hostinterface after frame parsing, frame slicing, error checking, saidreceive unit including:a detect ordered set unit for receiving decodedwords from said decode unit and detecting primitive signals, primitivesequences, and frame delimiters, a receive pipeline for recovery decodedwords from said decode unit, a CRC unit for generating CRC bits forincoming frames from said receive pipeline and checking for correct CRCbits, a multiplexer for recovering data from said receive pipeline fortransmission downstream, a steering control unit for providing logicsignals for frame parsing and steering, a frame interface formats (FIF)converter for converting Fibre Channel Standard format to FIF format, aframe control unit for providing frame parsing information for use incustom steering, a base address register for providing a base addressfor vectoring frames to a memory, and a receive control unit coupled toand controlling all other units of said receive unit, and providing allrequired status signals to downstream logic; d) a transmit unit coupledwith said encode unit for frame construction, CRC generation, FibreChannel primitive signal and sequence generation, said transmit unitincluding:a header multiplexer for multiplexing frame headers frommultiple sources, a frame data multiplexer unit connected to said headermultiplexer and receiving payload and link inputs and multiplexing dataand headers of frames, a CRC generate unit connected to receive outputsfrom said frame data multiplexer and generating a CRC for frames, anoutput multiplexer connected to receive outputs from said CRC generateunit and including data paths for header and data, for start of frameSOF and end of frame EOF delimiters, and CRC, said output multiplexerpresenting transmission words to said encoder through said arbitratedloop, a hardware sequencing parameters and registers unit for providingnecessary parameters for hardware managed sequences to said headermultiplexer, a unit for performing primitive signal, sequence, anddelimiter generation, a flow control unit for hardware managed flowcontrol and responsive to a R₋₋ RDY (receive unit ready) signals from aremote link receiver, and a transmit control unit interconnected withand controlling all units in a transmit operation including singleframes from said frame data multiplexer unit, sequences of frames in ahardware managed sequencing, idles and primitive sequences, buffer tobuffer flow control, frame delimiter generation, offset generation, andCRC generation and transmission for end of frame transmission; e) anarbitrated loop coupled to said decode unit, said encode unit, saidreceive unit, and said transmit unit, said arbitrated loop unitperforming all arbitration functions including recognition of primitivesignals and sequences pertinent to said loop, said arbitrated loopincluding:a loop state machine for performing loop initializationprotocol, loop arbitration and loop fairness in accordance with FibreChannel specifications, a first multiplexer controlled by said loopstate machine for receiving and transmitting decoded data from saiddecode unit, a second multiplexer controlled by said loop state machinefor receiving and transmitting data from said transmit unit for port toport communication, and a loop buffer connected with said loop statemachine for receiving all retiming received words.